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THE DAILY INDEX

Technology, AI, software, security, crypto and business

GENERAL

TLDR Hardware

ONSEMI REPLACES TINY WIRES INSIDE POWER CHIPS TO CUT ENERGY LOSSES

Onsemi's new Embedded Power Platform (EPP) builds power components directly into the silicon itself, wiring them together with precisely etched layers instead of the usual wire bonds, which cuts electrical losses and lets the parts switch faster. The idea is to design the electrical, thermal, and mechanical sides of a power system together from day one instead of separately, since treating them as separate problems has been forcing expensive redesigns late in development as devices demand more power in less space.

NVIDIA GRAPHICS CHIPS CONTAIN UP TO 40 TINY PROCESSORS FOR HOUSEKEEPING

The shader cores that do actual graphics work aren't where the RISC-V lives - it's in a collective of small management processors handling clocking, memory, security, and other housekeeping, with Nvidia VP Frans Sijstermans confirming each GPU packs 10 to 40 of them depending on the model. Users can't program these cores directly, and they're cryptographically locked down so tightly the GPU firmware won't even boot if they've been tampered with.

HUGE AI MODELS CAN RUN ON A CONSUMER GRAPHICS CARD BY USING SSD STORAGE

Mixture-of-Experts models keep growing capacity by adding more experts, but even after quantization, the full expert pool still dwarfs consumer RAM and VRAM, so local inference has to lean on SSD storage instead - a much harder problem than just having enough disk space. SSD-LLaMA builds an SSD I/O pipeline tuned specifically for fetching experts, layered with a three-tier SSD-RAM-VRAM hierarchy that dynamically decides which experts to hold where, and CPU-GPU hybrid execution balanced against the SSD's limited bandwidth, all while running every selected expert in full rather than pruning or substituting cheaper approximations.

INVISIBLE CHANGES TO A ROBOT'S TRAINING WORLD CAN MAKE IT FAIL IN REAL LIFE

Every 3D asset in a robot simulator carries two geometries - a visual mesh for rendering and a coarser collision mesh for physics - a legitimate gap since matching them exactly is too expensive. This paper shows that gap is exploitable: an attacker can alter only the collision mesh, so a policy trained on the poisoned asset looks and behaves normally in simulation, then fails or creates real safety risks once deployed. It slips past existing checks entirely, since asset review covers malware, copyright, and format, but nothing verifies visual-collision consistency, and the researchers found the defenses they tested weren't enough to catch it.

INTEL VETERANS RAISE $100 MILLION TO HELP DIFFERENT AI CHIPS WORK TOGETHER

Delos Data, founded by Intel veterans, raised $100 million led by Matrix Partners and Playground to build networking chips and software that move data faster between processors inside increasingly heterogeneous AI data centers. Early AI data centers were mostly Nvidia GPUs wired together with Nvidia's own proprietary networking, but as the focus has shifted from training toward running persistent, failure-tolerant agentic inference workloads, data centers now mix GPUs, XPUs, accelerators, CPUs, memory, and storage from Nvidia, AMD, Cerebras, and others, none of which were designed to talk to each other efficiently at that scale.

LEAKED TEST SUGGESTS APPLE'S M6 IS 27% FASTER THAN M5 ON MULTICORE TASKS

An unverified Geekbench 7 result for Apple's new 2nm M6 chip, debuting in the new Mac mini, shows a single-core score of 4,071 and a multi-core score of 22,783, up roughly 12% and 27% respectively over the M5's average scores. That single-core number tops every other Mac or PC in the Geekbench database, including the M5 Max (3,731) and Qualcomm's Snapdragon X2 Elite Extreme (3,396), backing up Apple's claim that the M6 has the world's fastest single-threaded CPU performance, while the multi-core gain lines up with Apple's advertised 1.2x multi-threaded improvement.

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