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THE DAILY INDEX

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AGILITY ROBOTICS UNVEILS DIGIT 5 HUMANOID BUILT FOR COOPERATIVELY SAFE WORK AT SCALE

Agility Robotics has introduced Digit 5, a next-generation humanoid robot featuring a 50-pound payload capacity, swappable end-effectors, and a rapid nine-minute recharge capability. The system incorporates a holistic safety architecture powered by onboard sensors and advanced safety controllers to autonomously slow down, avoid, or stop when people are detected nearby.

NVIDIA OPEN-SOURCES OSMO TO ORCHESTRATE TRAINING, SIMULATION, AND ROBOT TESTING FROM ONE YAML FILE

NVIDIA OSMO is an open-source, Kubernetes-native Physical AI orchestrator that connects data generation, RL training, simulation, evaluation, and hardware-in-the-loop testing across heterogeneous compute. Developers describe the pipeline in one YAML file, while OSMO schedules work across data-center GPUs, RTX simulation systems, cloud infrastructure, and edge platforms including Jetson and Arm. The system also exposes pipeline state, datasets, and available GPU capacity to coding agents.

OPEN SOURCE SAFETY CONSORTIUM FOR PHYSICAL AUTONOMY LAUNCHED

Move fast and break things is great, until your robot hurts a person. Creating robots that can safely operate around people is incredibly important, but it is also incredibly time-consuming and expensive. The Open Source Safety Consortium aims to fix this using open source. The consortium is an industry collaborative initiative dedicated to defining standardized safety frameworks, reproducible verification procedures, and validation benchmarks for open-source physical AI software stacks. The organization is attempting to bridge the gap between open-source robotic software innovation and rigorous industrial safety certifications. The hope is that future robotics projects can use turn-key products and libraries to build safe robots out of the gate.

META SAYS ITS THIRD-GEN IN-HOUSE AI CHIP BEATS NVIDIA ON EFFICIENCY, DEPLOYING BY EARLY 2027

Meta shares rose after Bloomberg reported the company plans to deploy its third-generation MTIA chip, internally called MTIA 450 or Arke, in data centers during the first half of 2027, with the next version, MTIA 500 (Astrid), set to finish design in about a month and reach data centers by the end of 2027. Twelve new sample chips arrived from TSMC on September 1 performing within 2-3% of simulations, and Yee Jiun Song, the VP overseeing Meta's custom silicon program, said each generation delivers better performance per watt and per dollar than current Nvidia offerings running the same AI models. Meta is developing the chips with Broadcom on design and TSMC on manufacturing, part of a broader push to diversify its silicon supply and reduce reliance on Nvidia.

ASTERA LABS' NEW LEO X CONTROLLER LETS MEMORY EXPANDERS PLUG DIRECTLY INTO AI ACCELERATOR FABRIC NETWORKS

Astera Labs' second-gen Leo 2 CXL memory controllers move from PCIe Gen5/CXL 2.x to Gen6/CXL 3.2 and double memory channels from 2 to 4, doubling both bandwidth and total capacity to up to 768GB of DDR4 or 4TB of DDR5 per expander, with new RAS features like hardware DIMM testing and soft-ECC on top of hardware ECC, aimed at economically reusing cheap, aging DDR4 pulled from retired servers rather than buying expensive new DDR5 amid the ongoing memory shortage.

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