Google has opened preorders for Googlebook, its new premium laptop category built on Android with ChromeOS-derived foundations under the official OS name Googlebook OS, five launch models from Acer, ASUS, Dell, HP, and Lenovo priced at $899-$1,299, hitting US shelves October 4. The lineup runs on Intel Core Ultra Series 3 or Snapdragon X Elite chips with 40+ TOPS NPUs (MediaTek-powered models to follow later), a 16GB RAM baseline with 32GB options, touchscreens up to 2.8K, and bodies built from aluminum, magnesium, or carbon fiber.
arstechnica.com·4 min read
At ROSCon 2026 in Toronto, Alphabet's Intrinsic released Intrinsic Core, an Apache 2.0-licensed, ROS-compatible set of robotics capabilities pulled directly from the same platform Intrinsic uses for real manufacturing deployments, aiming to lower the barrier for developers building industrial robotics applications. The package includes a hardware-agnostic real-time control framework that lets robots dynamically adapt mid-trajectory to sensor input, 6-DoF pose estimation built on NVIDIA FoundationPose for handling parts without rigid physical fixtures, automatic motion and grasp planning, Gazebo-powered simulation, camera calibration, and pre-tuned ROS drivers for supported robots, grippers, and 3D cameras.
Meta's Petal cable will span roughly 7,000km between France and the US, carrying 1 petabit per second, double the capacity of any subsea cable at transatlantic distance, becoming the first system to deploy multi-core fiber at scale. Since the 2010s, coherent optical transmission pushed fiber capacity 10x before hitting the Shannon Limit, forcing the industry toward spatial division multiplexing, adding more fiber pairs to a cable, which Meta scaled from 8 pairs on Marea to 24 on Anjana. Rather than pushing to 48 fiber pairs or widening the optical band, Petal packs 2-core fiber into a 24-pair system, physically equivalent to 48 pairs but using ultra-pure synthetic silica and carefully controlled refractive-index differences between the cores to keep crosstalk nearly immeasurable.
engineering.fb.com·5 min read
CXMT said its fifth-generation DRAM platform has entered mass production, claiming process capability "on par with the most advanced mass-produced nodes out there in the industry." The company reduced the spacing of key data-storage structures to 11.95 nanometers using "quadruple patterning," a technique that repeats manufacturing steps to produce finer circuit patterns without needing EUV lithography, and says the new platform yields at least 50% more dies per wafer than its fourth generation on an 8-gigabit baseline.
links.tldrnewsletter.com·3 min read
NVIDIA released Isaac ROS 5.0 at ROSCon in Toronto, adding support for ROS Lyrical and Ubuntu 24.04 and contributing a vendor-neutral accelerated memory transport interface to ROS Lyrical alongside the Open Source Robotics Alliance, giving the broader 1.3-million-user ROS community a standard way to move data efficiently across different compute hardware, including GPUs.
blogs.nvidia.com·5 min read
Most LLM chip-design agents work directly at RTL, the low-level hardware description that specifies exact circuit behavior, which forces the agent to grapple with fine-grained optimization details from the very start. This paper tests whether letting agents design at a higher abstraction level first, High-Level Synthesis (HLS), which compiles from something closer to software code down into RTL, produces better results, comparing four workflows including a combined approach called Agent-based HLS with RTL Refinement (AHRR): the agent designs in HLS, then a separate refinement pass drops down to RTL to recover optimizations the higher-level abstraction misses.