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TLDR Hardware

TLDR HARDWARE 2026-08-26

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01GENERAL

OPENAI CLAIMS CUSTOM JALAPEÑO CHIP BYPASSES NVIDIA GB300 IN EFFICIENCY BENCHMARKS

OpenAI announced that its custom-designed AI inference processor, dubbed Jalapeño and developed in partnership with Broadcom, outperformed Nvidia's flagship GB200 and GB300 systems in internal benchmark evaluations. The custom silicon demonstrated a 1.5x to 1.9x improvement in workload throughput per watt alongside a 1.7x to 3.6x reduction in response latency across frontier reasoning and open-weights workloads like GPT-OSS, DeepSeek R1, and Kimi K2.5

newsletter.semianalysis.com3 min read

D-MATRIX STACKS LOGIC ON 3D DRAM TO TARGET 100 TB/S INFERENCE BANDWIDTH

d-Matrix's Raptor accelerator stacks an N4 logic die directly on 3D DRAM and uses stream blocking, pinless data-bus inversion, thermal-aware refresh, and bank chaining to hold bandwidth near 100 TB/s. The company claims a 72-card rack can serve a 3-trillion-parameter-class model at 1M context at roughly 1,000 tokens per second per user, but the live Hot Chips report explicitly says working-system evidence and drawbacks remain to be shown.

servethehome.com7 min read

SAMSUNG ZHBM: DIRECT 3D DRAM STACKING REPLACES SILICON INTERPOSERS

Samsung detailed its vision for evolving HBM base dies from passive interposers into active logic, culminating in "zHBM." By using hybrid copper bonding to mount DRAM stacks directly onto the processor die, the architecture removes power-hungry SERDES layers, cutting package power by ~100W on a 1,200W accelerator while boosting memory bandwidth.

servethehome.com3 min read

NVIDIA INTRODUCES JETSON ORIN NANO 2 FOR ENTRY-LEVEL EDGE AI

NVIDIA's Jetson Orin Nano 2 is a lower-cost computer for robotics and edge inference. The module packages GPU compute, memory, and the Jetson software stack so builders can prototype perception and control without a server connection. Performance and efficiency figures are first-party, and suitability depends on the actual model and power envelope.

nvidianews.nvidia.com4 min read

SKILD AI'S S1 LEARNS 10-MINUTE ROBOT TASKS FROM A SINGLE VIDEO, NO FINE-TUNING

Skild AI's S1 is a foundation model that performs in-context learning for robotics, meaning it can be shown a single video of a long-horizon task, over 10 minutes long and never seen during pre-training, and then execute it without any fine-tuning. It's a meaningful step beyond typical robot foundation models, which usually need dedicated training data for each new task rather than picking one up on the fly from a single demonstration. This fits a broader pattern this year of general-purpose robot models learning tasks purely from examples, following similar early demos from Rhoda and Generalist, with Skild's version notably extending the horizon out to a full 10 minutes.

digg.com3 min read

FIGURE AI LAUNCHES INDEX, TRAINING ITS ROBOTS ON 16 MILLION CROWDSOURCED UPLOADS

Figure AI has come out of stealth with Index, a crowdsourced data platform that's already collected 16 million video uploads from over 264,000 app downloads across 108 countries, paying contributors $15 million so far to film themselves doing everyday tasks like opening drawers or folding laundry. The bet addresses robotics' core data bottleneck: language models could train on internet text, but embodied AI needs real-world physical demonstrations that simply don't exist online at scale. Figure is committing over $1 billion to data and compute over the next 12 months to close that gap.

glitchwire.com4 min read

02MISCELLANEOUS

IBM UNVEILS NEXT-GENERATION DUAL-ARCHITECTURE PROCESSOR FOR IBM Z AND LINUXONE

IBM announced its first dual-ISA mainframe processor at Hot Chips 2026, engineered to natively execute both IBM z/Architecture and Armv9.3-A instructions on the same physical cores. Fabricated on a 2nm process node, the chip features 11 high-performance cores clocked above 5.7 GHz, integrated AI inference acceleration, a dedicated on-chip Data Processing Unit (DPU) for I/O offload, and large enterprise cache tiers. Rather than using separate physical cores in a heterogeneous layout, each core dynamically switches between z/Architecture and AArch64 execution within nanoseconds, enabling organizations to run unmodified Arm-native Linux software and modern AI frameworks concurrently alongside mission-critical z/OS transaction systems.

newsroom.ibm.com3 min read

FIRST LOOK INSIDE APPLE'S AI SERVERS REVEALS A DENSELY PACKED M-SERIES DESIGN

Leaked photos of a custom 2U rack server, reportedly from Apple's Houston manufacturing facility, show its Private Cloud Compute hardware for the first time. Each unit packs four columns of eight boards apiece (32 chips total), with a single Apple Silicon package at the center of each board flanked by removable brackets, all cooled by one fan per column pulling air front-to-back through a plastic-enclosed passage. Forum analysis of the board sizes suggests these are more likely base M5-class packages rather than the M5 Ultra chips previously rumored, since an Ultra package (two dies plus eight memory chips) would be roughly four times larger than what's visible in the photos, and the heatsinks look undersized for a 150-watt chip

appleinsider.com3 min read